EDA Netlist Writer report for DE0_NANO
Wed Aug 15 18:19:04 2018
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Aug 15 18:19:04 2018 ;
; Revision Name             ; DE0_NANO                              ;
; Top-level Entity Name     ; DE0_NANO                              ;
; Family                    ; Cyclone IV E                          ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                                           ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option                                                                                            ; Setting                   ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only                                                   ; Off                       ;
; Time scale                                                                                        ; 1 ps                      ;
; Truncate long hierarchy paths                                                                     ; Off                       ;
; Map illegal HDL characters                                                                        ; Off                       ;
; Flatten buses into individual nodes                                                               ; Off                       ;
; Maintain hierarchy                                                                                ; Off                       ;
; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
; Enable glitch filtering                                                                           ; Off                       ;
; Do not write top level VHDL entity                                                                ; Off                       ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
; Architecture name in VHDL output netlist                                                          ; structure                 ;
; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
+---------------------------------------------------------------------------------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Simulation Generated Files                                                                                                                  ;
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Generated Files                                                                                                                             ;
+---------------------------------------------------------------------------------------------------------------------------------------------+
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_6_1200mv_85c_slow.vo     ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_6_1200mv_0c_slow.vo      ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_min_1200mv_0c_fast.vo    ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO.vo                       ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_6_1200mv_85c_v_slow.sdo  ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_6_1200mv_0c_v_slow.sdo   ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_min_1200mv_0c_v_fast.sdo ;
; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/DE0_NANO_v.sdo                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
    Info: Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition
    Info: Processing started: Wed Aug 15 18:19:03 2018
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DE0_NANO -c DE0_NANO
Warning (125092): Tcl Script File DE_NANO_SOPC.qip not found
    Info (125063): set_global_assignment -name QIP_FILE DE_NANO_SOPC.qip
Warning (125092): Tcl Script File myfirstpll.qip not found
    Info (125063): set_global_assignment -name QIP_FILE myfirstpll.qip
Info (204019): Generated file DE0_NANO_6_1200mv_85c_slow.vo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_6_1200mv_0c_slow.vo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_min_1200mv_0c_fast.vo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO.vo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_6_1200mv_85c_v_slow.sdo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_6_1200mv_0c_v_slow.sdo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_min_1200mv_0c_v_fast.sdo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file DE0_NANO_v.sdo in folder "C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 4742 megabytes
    Info: Processing ended: Wed Aug 15 18:19:04 2018
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


